1. Field of the Invention
This invention relates to a method of making a V-MOS field effect transistor for a dynamic memory cell and, more particularly, to a method of making such a device which does not require epitaxial silicon growth as a step of the process.
2. Description of the Prior Art
MOS field effect transistors are formed by diffusing source and drain areas into a crystalline substrate, covering the substrate with an insulating layer and placing a conductive gate electrode material on top of the insulating layer between the source and drain areas. When the appropriate voltage is applied to the gate electrode, the resulting electric field causes a channel for charge carriers to be formed between the source and drain areas. Hence, the name field effect transistor. V-MOS field effect transistors are so called because the transistor is formed along the walls of a V-shaped groove or pit as distinct from previous planar field effect transistors. With conventional V-MOS technology, the source of the transistor is formed below the drain area thus reducing the amount of space required for each transistor on the surface of the crystalline substrate. Such V-MOS structures are disclosed, for example in the Rodgers, U.S. Pat. No. 3,924,265 and the Jenne, U.S. Pat. No. 4,003,036.
Since the drain area is placed above the source area in conventional V-MOS technology, additional process steps are generally required as compared to the planar MOS technology described above. In the existing V-MOS structures, an N-type source area is first formed by diffusion in a P-type crystalline silicon substrate, and then a separate layer of lightly P-doped silicon material is epitaxially grown over the source area. The N-type drain areas are formed in the epitaxial layer which is then covered with an oxide or other insulation, the V-notch or pit is etched, the gate insulator is grown or deposited and then the gate electrode layer is formed over the V. These extra steps involve unusually difficult process operations and additional time and thus increase the cost of the wafers from which the integrated circuit chips are formed. However, such a process does allow for the provision of a larger source area to provide increased source capacitance when the device being fabricated is a dynamic memory cell such as disclosed in the above-referred-to Jenne patent.
It is then an object of the present invention to provide an improved V-MOS field effect transistor.
It is another object of the present invention to provide an improved V-MOS field effect transistor that requires fewer and less difficult steps for fabrication.
It is still a further object of the present invention to provide an improved dynamic memory cell employing a V-MOS field effect transistor.